1. Technical Field
The present disclosure is related to a multi-supply dual port register file and, in particular, a multi-supply dual port register file adapted for first input first output (FIFO) use between different power domains.
2. Description of the Related Art
FIG. 1 shows a diagram of two domains 10, 12 coupled via an interface 14. Each domain 10, 12 may comprise electronic circuitry, which may be analog or digital circuitry. For example, the first domain 10 may be a processor, whereas the second domain 12 may be a system-on-chip (SoC) that is built around the processor and designed to work with the processor. The two domains 10, 12 may operate at different voltage levels. For example, the first domain may operate at a voltage level of 0.7 volts (V), whereas the second domain may operate at a voltage level of 0.8V. In addition, the two domains 10, 12 may operate at different frequencies. For example, the first domain 10 as a processor domain may operate at a higher frequency of 1.5 gigahertz (GHz), whereas the second domain, which is the SoC may operate at a lower frequency of 500 megahertz (MHz). Furthermore, the first domain 10 and the second domain 12 may be in different power domains. The first and second domain 10, 12 may be in different power domains if they can each be 10, 12 selectively switched off or if the supply voltage of one domain 10, 12 is not connected (or shorted) with the supply voltage of the other domain 10, 12. Accordingly, the two domains 10, 12 may be supplied with the same voltage level but remain as two independent power domains.
As shown in FIG. 1, the domains 10, 12 are each coupled to the interface 14. The interface 14, which is bidirectional comprises a first unidirectional interface 14a and a second unidirectional interface 14b. Although the bidirectional interface is shown in FIG. 1, any unidirectional interface 14a,b may alternatively be used. The interface 14 may be used for transferring data between the domains 10, 12. The bidirectional interface 14 or the unidirectional interfaces 14a,b may be a register file, such as a dual-port register file, a bridge or a first-in first-out (FIFO queue), among others. The first domain 10 may supply data to the first unidirectional interface 14a (for example, by writing data to the interface 14a) and the second domain 12 may read the data from the interface 14a. The interface 14a may enable voltage, clock or power domain crossing, whereby data of the first domain 10, which operates at a different voltage or clock frequency than the second domain 12 or is in a different power domain than the second domain 12, may be supplied to the second domain 12 and vice-versa. The interface 14a may accordingly facilitate domain crossing between voltage, clock or power domains.
FIG. 2 shows a diagram of the two domains 10, 12 electrically coupled via an interface 14a. The interface 14a comprises a plurality of data elements 16a-d (collectively referred to herein by the numeral alone), a multiplexer 18, a voltage level shifting and power isolation unit 20, write control logic 22 and read control logic 23. Data of the first domain 10 is written using write control logic 22 to the interface 14a and read by the second domain 12 from the interface 14a using read control logic 24.
The first domain 10 outputs, to the write control logic 22, data to be sent to the second domain 12. The write control logic 22 provides the data to one or more of the plurality of data elements 16. For example, each data element 16 may be a flip-flop and may receive one bit of data from the write control logic 22 and store the bit. Thereafter, the bits stored by the plurality of data elements 16 are outputted to the multiplexer. It is noted that although a plurality of data elements 116 are shown in FIG. 2, only one data element may be used. The write control logic 22 may also receive a read pointer signal 26 from the read control logic 24 and send a write pointer signal 28 to the read control logic 24. The read pointer signal 26 and the write pointer signal 28 may be used to synchronize a timing of data reading and writing and/or to indicate placement of an ordering of the storage of the bits in one of the plurality data elements 16.
The read control logic 24 outputs a selection signal 30 to the multiplexer 18. Based on the selection signal 30, the multiplexer 18 outputs a selected data bit from a data element 16 to the voltage level shifter and power isolation unit 20. The voltage level shifter and power isolation unit 20 modifies the voltage level of the selected data bits to be compliant with that of the second domain 12. For example, if the voltage level of the first domain is 0.7V whereas the voltage level of the second domain 12 is 0.8V, the voltage level shifter and power isolation unit 20 outputs a voltage level-modified data bit to the second domain 12. Continuing with the example, the voltage level of the outputted data bit is 0.8V and in accordance with the second domain 12. Level shifting slows the operation of the interface 14 and introduces delay in the data transfer between the two domains 10, 12.
It is noted that shifting the voltage level of the data from a voltage level of the first domain 10 to a voltage level of the second domain 12 increases the latency of the data transfer through the interface 14a. In alternative implementations, the voltage level shifter and power isolation unit 20 may be in the data path between the plurality of data elements 16 and the multiplexer 18. However, that results in increasing the size of the interface 14a circuitry due to the fact that a plurality of data bits are each voltage level-shifted prior to being provided to the multiplexer 18.
It is desirable to have an interface that provides efficient data transfer between isolated power domains, such as power domains that operate at different voltages or frequencies.